1. name and explain the 3 main sub-components of the Control Unit
- instruction register – hold the current instruction
- instruction/program counter (IC/PC) – refers to next instruction to be fetched from memory
- instruction decoder – decodes instruction to be executed by the ALU
What is a Functional Unit? Name 4 common types of FUs
Die Aufteilung der Operanden bei scalaring (int, addressing, floating, comparing) Einige Recheneinheiten (FUnctional Units) sind für spezielle Operationen zuständig.
What’s the difference between a Barrel Shifter and a Matrix Multiplier?
Barrel Shifter: uses multiple 1-bit adders and AND-gates to multiply two integer numbers
Matrix Multiplier: contains a ROM-table, whose cells are directly selected by the operands of the multiplication (row/cell) – the corresponding row/cell-crossing contains the multiplication result (no calculation, result is only read)
What does Amdahl’s law tell us? Give an illustrative example
Amdahl’s law is about how much performance-boost you get from additional CPU-Cores. It depends in the programmer on how many percent of his program is parallelizable, E.g. if a program is parallelizable for 10% it would make a significant difference for this part, but the rest of the program would take the same time.
What is NVRAM? Name two possible ways to implement NVRAM
NVRAM is a type of RAM which doesn’t lose its content on power-cut. There are 2 maminly different ways to get NVRAM: 1. The combination of SRAM and a Lilon battery. Or 2. Using various physical effects in order to store data, once stored it doesn’t matter if it got power or not.
Explain the concept of super-pipelining. How does it relate to super-scalar CPUs?
While super pipelining, each stage of an instruction is divided into smaller steps allowing the CPU to superpipeline the tasks. It still completes one instruction per cycle but it manages more cycles per second.
While Super-scalaring tasks are divided into different operations like, Integer ops, float ops, test(branch) or addressing. Each operation has an individual functional unit which handles this.
There are super-pipelined super-scalar CPUs available today which combine both functions.
Explain the concept of Out-of-Order Execution (OOO)
- CPU does the reordering in hardware (at runtime)
- Here the CPU looks at a group of instructions, and reorders them so that the pipeline is filled as much as possible with instructions surely needed
- Must be done without altering program logic or violating inter-dependencies – Out-of-order Execution/ Dynamic instruction scheduling
Describe how a 1-Bit memory cell works. How does it differ from a 1-bit dynamic memory cell?
A static memory cell needs up to 5 or 6 transistors, in order to enable writing W/R and “select” must be set to “1”. The dynamic memory cell has a far simpler design, it only consists of data-line, read/ wirte-line, one transistor and one capacitor. (The dynamic memory cell is cheaper to produce, that’s the reason it is mainly used in comparison to the more rliable static cell.
What’s the difference between synchronous and asynchronous buses? What type is usually used in modern computer systems?
Synchronous buses have an oscillator which clocks at range from 5-300 MHz and hence is slower than a typical modern CPU.
Asynchronous buses have a master & slave-synchronization and have to meet in order to get a “synchronized handshake”, then a clock for both components is agreed.
Most buses are synchronous due to simplicity in design, implementation, and communication
Describe the two common types of branch prediction and name their advantages and disadvantages. What is the mispredict penalty?
-static branch prediction: the compiler marks the branch at compile time it thinkswill be more likely to occur and the CPU will follow the mark.
-dynamic Branch rediction: here the CPU describes at program-runtime which branch to take, using the o chip “Branch prediction table”
“if I guessed wrong” – this alredy executed instructions are useless, and the CPU has to start at the begin of the other branch.
“if I guassed right” – the CPU can continue at full speed.
-Mispredict Penalty: instructions to be canceled, if guessed wrong
Name the 5 possible states of Linux user-space process
R(Running): running or runnable
D(Uninterruptible sleep): in I/O
S(Interruptible sleep): Waiting for event to complete
Z(Defunct/ Zombie): Terminated but not reaped by parents
T(Stopped): Task is currently stopped
Explain the cooperative interaction between CPU, memory management unit, translation look - aside buffer and hard-disk
Since modern CPUs use multi-level page-tables, access on a page would mean a huge performance loss (would have to access at least 2 tables before getting to the physical memory address)
Therefore the Translation Lookaside Buffer is a cache inside the CPU which contains the most frequently used page table entries. If not in TBL the requested page table gets stored in the TLB
Under what circumstances is a program called relocatable?
When relative memory addressing is been done
= base address + offset
1. What is the multi-level feedback queue?
Processes are separated in different queues. (high or low priority)
Some sort of feedback tells if it needs to change the queue at runtime
Describe the Linus user address space (process memory layout). List all memory segments, and describe for what types of data they are used for, respectively
· Region at very top of virtual address space
· Stack grow down in memory
· Stack is a LIFO structure (Last in, first out)
- Items are pushed on stack (add on top of stack – lowest address)
- Items are popped from stack (top element is removed)
- Can only pop top element at any time, nothing in between
Memory Segments:
· Stack – used for function-local variables
· Heap – is for dynamic allocation
· .bss – contains any non-initialized data
· .data – contains any initialized data
· .text – contains executable code
a. Explain how a function call works in Assembly
Ausführung einer Funktion
- Speichern des Base Pointers (EBP)
- Push on Stack
- Base Pointer aktualisieren
- Kopieren von ESP zu EBP
ð Bereich zwischen EBP und ESP wird als Stack Frame einer Funktion bezeichnet
b. what does the stack look like after a function-call using 3 string-arguments, with the function declaring 2 function-local .long variables?
c. Show how arguments and local variables can be accessed
Addition der Anzahl von benötigten Byes für die Argumente vom EBP
Subtraktion der Anzahl von benötigten Bytes für die lokale(n) Variable(n) vom EBP
Explain how a scheduler with dynamic re-prioritization and deadline scheduling works
· Low-priority process enters run-queue and is assigned with deadline time td
· If td/2 has passed without process being run – priority + 1, td is halved
· Guarantees process is run within deadline
What are the main differences between MBR und GPT?
MBR: max 4 primary partitions; a single partition is limited to 2 TiB of storage (232 disk blocks, 512 bytes each)
GPT: (theoretically) unlimited number of partitions (Windows: max 128); each partition can hold up to 1.000.000 TiB (264 disk blocks)
What is Thrashing and in what situation can it occur?
When a CPU needs more time for paging and swapping pages and make sure the right page is available, then it is able to use for processing. This event is called thrashing. The working set is introduced, it holds all frames a current process needs to run smooth. To avoid Thrashing every process is assured to have the frames within its working set swapped in.
What is the purpose of a multi-level page and how does it work? What’s the dirty-bit used for
The page table is used to translate from virtual to physical memory-addresses. (from pages to frames) Nowadays we have much larger memory and larger word sizes, a single page table would not be enough. Page Table is split into Page Directory (Outer Page Table) and actual Page Table (Inner Page Table) – Page Directory “refers” to Page Tables
The dirty bit gives information if the page has been swapped out to secondary storage like hard-drive.
Last changeda year ago
