IC

Q: What is CMP?

EN: CMP = Chemical Mechanical Polishing

It smooths and flattens the wafer surface in chip production.Why? → To make sure the next layers are built on a flat surface.

CMP is a removal process in which materials are moved from a wafer surface by the combination of

mechanical grinding and wet chemical reaction.

• Commonly used CMP processes are silicate glass CMP, tungsten CMP, and most recently copper CMP.

• Timely post-CMP cleaning is a critical step to ensure the yield of CMP processing; therefore, some CMP tools

are integrated with wet clean stations to form the so-called dry-in/dry-out CMP systems.

• The purpose – very smooth planar surfaces

EN: The Float Zone method produces ultra-pure silicon → because it avoids contact with a crucible, so no contamination. 💡 Main advantage: Higher purity than CZ silicon.

DE: Die Float-Zone-Methode erzeugt ultrareines Silizium → weil kein Tiegel verwendet wird → keine Verunreinigung. 💡 Hauptvorteil: Höhere Reinheit als CZ-Silizium.

STI = Shallow Trench Isolation

Used to separate transistors on a chip.

It creates trenches in the silicon, fills them with oxide, and isolates devices.

✅ Advantages:

Better isolation than older methods (like LOCOS)

Saves space → enables smaller transistors

Less leakage and interference

EN: STI is a trench-filled isolation that allows tight, clean separation between transistors.

DE: STI ist eine mit Oxid gefüllte Grabenisolation, die Transistoren sauber und platzsparend trennt.

• Resolution (smaller device structures)

• Exposure field ( chip size increases)

• Placement accuracy (alignment)

• Throughput (cost)

• Defect density (mask, photoresist and process) (influences the yield loss, cost)

An aerial image is the light intensity pattern that forms on the wafer during photolithography, just before the photoresist is exposed. It’s created by light passing through the photomask and lens system.

📸 It’s like a shadow projection of the mask pattern – but with some blurring and diffraction effects.

EN: The aerial image is the light pattern formed on the resist, shaped by the mask.

DE: Das Aerial Image ist das Lichtmuster auf dem Lack, das durch die Maske entsteht.

Latent image is the 3D replica produced by chemical processes in the resist.

EN:

A phase-shift mask changes the phase of light in certain areas of the mask by 180°.

This causes destructive interference at the edges of features.

→ The contrast between light and dark is sharper → sharper image in the resist!

💡 Imagine two waves canceling each other out to make the edges clearer.

➡️ Robert Noyce's work is closer to today’s IC process. Why? Because he used planar technology and photolithography, which are the basis of modern IC manufacturing.

✅ Noyce's design was scalable, used silicon, and allowed mass production. 🛠️ Kilby used germanium and wire connections – not suitable for scaling.

EN: A 4-point probe measurement is used to measure resistivity (or sheet resistance) of a material, especially thin semiconductor layers.

🔌 It uses 4 probes:

• The outer two inject current

• The inner two measure voltage This avoids errors from contact resistance and gives more accurate results.

✅ We need it to precisely measure electrical properties of materials during fabrication.

EN:

LDD = Lightly Doped Drain

It’s a technique used in MOSFETs to reduce electric field strength near the drain and prevent hot carrier effects.

💡 The drain is split into:

A lightly doped region (closer to the channel)

A heavily doped region (farther out)

✅ Main function:

Reduce damage from hot electrons

Improve device reliability and lifetime

PSG = Phosphosilicate GlassIt’s a silicon dioxide (SiO₂) layer that contains phosphorus.

Commonly used in semiconductor device fabrication for intermetal layers, i.e., insulating layers deposited

between succeedingly higher metal or conducting layers, due to its effect in gettering alkali ions.

Gettering = removing unwanted impurities (like metals) from active areas. It relocates them to harmless regions of the wafer.

🔁 Three main steps:

1. Contaminant Release → Impurities become mobile (e.g., via heating)

2. Contaminant Transport → Impurities move through the wafer (via diffusion)

3. Contaminant Capture → Impurities are trapped in a “gettering site” (e.g. PSG, backside damage, or oxide)

a)

thickness(d) sinks -> Cox rises (Cox=epsi/d) ->Qm sinks

Therefore, the thinner the gate Oxide is, the smaller the impact of Sodium Contamination will be.

b)

• Freezeout region – a region where the donor ions are situated at the donor level, but the free electrons are unable to move due to the 0 Kelvin temperature

• Extrinsic region – a region relatively constant over operating range, electron mobility has increased

• Intrinsic region – a region at processing temperatures where intrinsic carrier levels dominate

A – vacancy, B – interstitial, C – substitutional larger atom, D – substitutional smaller atom, E – Frenkel pair

• Gate dielectric thickness and material

• Gate and substrate materials

• Interface charge (gate to gate dielectric, gate dielectric to substrate)

• Dopant concentration underneath gate – VT adjust implantation

✅ EN:

1. Substrate Doping Concentration (Nₐ or N_d) → Higher doping → increases Vₜₕ → Lower doping → decreases Vₜₕ

2. Gate Oxide Thickness (tₒₓ) → Thinner oxide → increases Cₒₓ → lowers Vₜₕ → Thicker oxide → decreases Cₒₓ → raises Vₜₕ

💡 Bonus:

• Work function difference (φₘ - φₛ)

• Channel implants (e.g. Vₜₕ adjust implants)

⚡️ EN:

Hot electron effect = Occurs when electrons in a MOSFET gain very high energy due to strong electric fields near the drain (especially in short-channel devices). ➡️ These “hot” electrons can injected into the gate oxide, causing:

• Oxide damage

• Vₜₕ shift

• Device degradation

✅ How to eliminate or reduce it:

1. LDD (Lightly Doped Drain) structure → Reduces electric field near the drain

2. Lower supply voltage → Less acceleration → fewer hot electrons

• Also called short channel effect occurs when a high voltage is applied across the source and drain of a device,

the electric field is high, and the electrons are accelerated in the channel

• Lightly doped drain can reduce this effect due to gate voltage magnitudes and electric fields

• In electronics, short-channel effects occur in MOSFETs in which the channel length is comparable to the

depletion-layer widths of the source and drain junctions. These effects include, in particular, drain-induced

barrier lowering, velocity saturation, and hot carrier degradation.

• AFM

• SEM

• Colour Chart

• Ellipsometry

• Reflectance

• C-V measurement

✅ EN:

1. Ellipsometry → Measures change in polarized light reflection → Very precise for thin films (nm range)

2. Spectral Reflectance (Interference Method) → Uses color interference from reflected light → Quick and non-destructive

3. Etch Rate / Step Height (Profilometry) → Etch part of the oxide, measure step with a profiler → Direct and physical thickness measurement

4. Capacitance Method (C-V Measurement) → Uses MOS capacitor structure → Calculates thickness from oxide capacitance CoxCox​

5. SEM (Scanning Electron Microscopy) → Cross-section imaging at high resolution → Useful for thick layers or when visual confirmation needed

EN: Performance depends on optical setup, mask quality, light wavelength, and mechanical stability.

✅ EN: Key Performance Factors

1. Resolution (R) → Depends on wavelength (λλ) and numerical aperture (NA):

   R=k1⋅λNAR=k1​⋅NAλ​

2. Depth of Focus (DOF) → Tolerance for wafer surface unevenness:

   DOF=k2⋅λNA2DOF=k2​⋅NA2λ​

3. Wavelength of Exposure Light → Shorter wavelength = better resolution (e.g. DUV, EUV)

4. Numerical Aperture (NA) of Lens → Higher NA = better resolution, but lower DOF

5. Lens Aberrations → Imperfections in the lens reduce pattern fidelity

6. Mask Quality and Alignment → Mask defects or misalignment → printing errors

7. Vibration and Stage Stability → Wafer movement during exposure blurs the image

8. Resist Sensitivity and Process Conditions → Affects how well the aerial image is transferred

DUV uses deep UV light to expose a special resist layer that’s later developed to transfer patterns.

✅ EN:

DUV = Deep Ultraviolet → Light with wavelengths ~193–248 nm → Common sources: KrF (248 nm), ArF (193 nm) excimer lasers

📸 DUV Exposure Process:

1. Coat wafer with DUV-sensitive photoresist

2. Align photomask with wafer

3. Expose with DUV light → chemical bonds in the resist break (for positive resist)

4. Post-exposure bake (optional)

5. Develop the resist → exposed areas are removed (positive tone)

• Contact printing is capable of high resolution but has unacceptable defect densities (minimal diffraction effects, low cost, contact contaminants and defects)

• Proximity printing cannot easily print features below a few μm (diffraction effects exist, may be used for x-ray systems)

• Projection printing provides high resolution and low defect densities and dominates today (diffraction a concern)

The pull rate is how fast the crystal is pulled vertically from the melt. The crystal diameter depends on the balance between heat removal (cooling) and pull speed.

📉 If pull rate ↑ → diameter ↓ 📈 If pull rate ↓ → diameter ↑

Why? Faster pulling gives less time for the crystal to grow wider, so it becomes thinner. Slower pulling allows the crystal to grow broader before being lifted.

EN: The Fermi function tells how likely an energy level is occupied by an electron.

✅ EN:

The Fermi Function f(E)f(E) gives the probability that an energy level EE is occupied by an electron at temperature TT.

f(E)=11+e(E−EF)/kTf(E)=1+e(E−EF​)/kT1​

Where:

• EE = energy level

• EFEF​ = Fermi level

• kk = Boltzmann constant

• TT = absolute temperature

🧠 At T=0T=0 K:

• f(E)=1f(E)=1 for E<EFE<EF​ (all states below EFEF​ are filled)

• f(E)=0f(E)=0 for E>EFE>EF​ (all states above EFEF​ are empty)

EN: MOS is a structure; MOSFET is a transistor that uses the MOS structure to control current.

EN:

• MOS = Metal-Oxide-Semiconductor → A structure consisting of a metal gate, oxide layer, and semiconductor substrate → It's the core of a MOS capacitor

• MOSFET = Metal-Oxide-Semiconductor Field Effect Transistor → A transistor that uses the MOS structure to control current → Has source, drain, gate, and channel → Used as a switch or amplifier

💡 A MOSFET contains a MOS structure, but not every MOS is a transistor.

p=n_i^2/n =10^20/10^15 = 10^5 cm^-3

✅ EN:

LOCOS = Local Oxidation of Silicon It’s a method to electrically isolate transistors on a silicon wafer.

How it works:

1. Cover active areas with Si₃N₄ (silicon nitride) → blocks oxidation

2. Leave other areas exposed

3. Thermal oxidation grows thick SiO₂ only in unprotected regions

4. This oxide becomes the field oxide → separates devices

📦 Purpose:

• Create isolation between transistors

• Prevent leakage currents

🧱 But: LOCOS causes “bird’s beak” effect – oxide spreads sideways under nitride → wastes space

• Local Oxidation of Silicon (LOCOS) is the traditional isolation technique.

• At first a very thin silicon oxide layer is grown on the wafer, the so-called pad oxide. Then a layer of silicon nitride is deposited which is used as an oxide barrier. The pattern transfer is performed by photolithography. After lithography the pattern is etched into the nitride. The result is the nitride mask, which defines the active areas for the oxidation process. The next step is the main part of the LOCOS process, the growth of the thermal oxide. After the oxidation process is finished, the last step is the removal of the nitride layer.

• The main drawback of this technique is the so-called bird's beak effect due to the high release stress problem (high-temp oxidation) and the surface area which is lost to this encroachment.

• The advantages of LOCOS fabrication are the simple process flow and the high oxide quality, because the

  whole LOCOS structure is thermally grown.

Line x loc=0 spac=0.5 (Initialize mesh with 0.5 um spacing)

Etch nitride left p1.x=1 (Etch nitride at etch location 1 um)

EN: Furnace oxidation is slow and for thick oxides; RTO is fast and for thin oxides.

• Furnace oxidation

o Slower

o Multiple wafers at the time

o Lower temperature

• RTP

o Faster

o One wafer at a time

o Higher temperatures

o Simple temperature feedback (pyrometer)

EN: SIMS is used to analyze elemental composition and depth profiles via ion sputtering.

SIMS = Secondary Ion Mass Spectrometry

🧪 Function: SIMS is an analytical technique used to measure the composition and depth profile of materials.

How it works:

1. A primary ion beam (e.g. O₂⁺ or Cs⁺) hits the sample surface

2. Secondary ions are ejected from the surface

3. These ions are analyzed by a mass spectrometer → You get elemental and dopant profiles with depth resolution

✅ Commonly used to:

• Detect dopant concentration in semiconductors

• Measure impurity levels

• Perform depth profiling (nm resolution)

EN: Oxide thickness can be measured non-destructively with ellipsometry or destructively via SEM cross-section.

✅ EN:

🔬 1. Non-destructive method: Ellipsometry

• Measures the change in polarization of reflected light

• Used on flat test areas with no nitride mask

• Accurate for thin and medium oxide layers ✅ No sample damage

🧪 2. Destructive method: SEM cross-section

• Wafer is cleaved and coated (optional), then imaged in a Scanning Electron Microscope

• Direct visual measurement of oxide thickness ✅ Very accurate, but sample is destroyed

✅ EN:

🔩 1. Edge Dislocation

• An extra half-plane of atoms is inserted into the crystal

• Distortion is perpendicular to the dislocation line

• Burgers vector ⊥ dislocation line 📌 Imagine a book with one extra page halfway in = stress above/below

🌀 2. Screw Dislocation

• Atoms are displaced like a spiral staircase

• Distortion is parallel to the dislocation line

• Burgers vector ∥ dislocation line 📌 Imagine cutting and shearing a crystal so it forms a helix

EN: The bleaching effect means the resist absorbs less light as exposure continues, improving depth uniformity.

• When the photoresist is exposed, it will slowly become transparent, allowing light to penetrate deep into the

photoresist and continue exposure.

• An effect occurring in DNQ resist as the resist is exposed, the PAC is altered. Absorbing less and less light –

becoming transparent. As the top layers are exposed, they transmit more light to the deeper layer.

✅ EN:

The bleaching effect occurs during photoresist exposure when the resist becomes less absorbing to light as it is exposed.

🔍 What happens:

• Initially, light is absorbed → triggers chemical reaction

• As exposure continues, the absorbing species break down → More light penetrates deeper into the resist → Exposure becomes more uniform throughout resist depth

✅ Result:

• Improves vertical profile

• Helps ensure full development of exposed regions

Extreme ultraviolet lithography

• 13.5 nm (beyond 1 um)

• We have super small resolutions now and to achieve it we need short wavelength light sources as for

example EUV

• Relatively flat profile – ks close to 1

• Much more variation in doping concentration along the crystal – ks<<1

• So A

EN: In N-type Si, Au acts as an acceptor because its acceptor level is below the Fermi level and captures electrons.

✅ EN:

Gold (Au) has both donor (E_D) and acceptor (E_A) levels, both near the middle of the silicon bandgap. In N-type silicon, the Fermi level EFEF​ is closer to the conduction band.

🔍 What happens?

• Au acceptor level lies below EFEF​ → it can accept electrons from the conduction band

• That means Au captures electrons, creating holes → So it behaves as an acceptor in N-type silicon

✅ Answer: Au acts as an acceptor in N-type silicon → It compensates electrons and can reduce conductivity

Au will behave as an acceptor in Ntype silicon. Because its D energy is smaller than the the fermi level of N

silicon, so it#s ability to donate electrons will also be small – it cannot be used as a donor.

• In other words, if the fermi level is higher than Au, electrons will easily migrate there, so it can be used as an

acceptor.

• Au’s ED is occupied – neutral – no electrons provided; Au’s EA is occupied by electrons – mass-electricity –

acceptor ??

• For the alkali ions, gettering generally uses dielectric layers on the topside (PSG or barrier Si 3 N 4 layers).

o Charge dipoles in PSG – affect E field

o PSG absorbs water vapor and causes Al corrosion

• For metal ions, gettering generally uses traps on the wafer backside (extrinsic) or in the wafer bulk (intrinsic)

EN: Flat substrates are critical in future lithography because DOF becomes smaller as resolution improves.

✅ EN:

As resolution improves, lithography uses shorter wavelengths (λ) and higher numerical aperture (NA).

This causes the depth of focus (DOF) to get smaller, because:

DOF=k2⋅λNA2DOF=k2​⋅NA2λ​

➡️ Smaller DOF means the resist layer must be very flat — even tiny bumps can push features out of focus, causing blurring or patterning errors.

✅ In the past (longer λ, larger DOF), small height differences were tolerable. But future lithography needs perfectly flat layers to stay within the narrow DOF window.