Petri Nets [True / False]: A Petri net N = (C, E, F) is called pure if the flow relation F does not contain any loops.
Correct Answer: True.
Explanation: In Petri net theory, a net is defined as pure if and only if it contains no self-loops of length 2, meaning there exists no pair (c, e) where both (c, e) in F and (e, c) in F. Loops of length >= 3 do not violate purity.
Petri Nets [True / False]: A Petri net is called simple if no two transitions have the same sets of preconditions and postconditions, and no two places have the same sets of pre-events and post-events.
Explanation: By definition, a net is simple if no two transitions share identical input and output places (*t1 = *t2 and t1* = t2* implies t1 = t2), and symmetrically for places. A trap is confusing 'simple' with 'pure' (which forbids 2-element self-loops).
Multi-Objective Optimization [True / False]: A Pareto set contains all Pareto-optimal solutions.
Explanation: The Pareto set (or Pareto front) by definition consists of all non-dominated design points in the design space. A distractor trap is claiming it contains only a single globally optimal trade-off point.
A/D Discretization [True / False]: The reconstruction of sampled signals without errors is possible if the sampling frequency is equal to the signal frequency (f_s = f_sig).
Correct Answer: False.
Explanation: The Shannon-Nyquist Sampling Theorem strictly requires the sampling frequency to be strictly greater than twice the highest frequency component (f_s > 2 * f_max). If f_s = f_sig, fatal aliasing occurs and complete waveform information is lost.
Real-Time Operating Systems [True / False]: Semaphores are used to protect critical sections.
Explanation: Semaphores are fundamental synchronization primitives used to ensure mutual exclusion so that only one task accesses a shared critical resource at a time. The common pitfall is confusing mutex protection with thread scheduling.
Evaluation [True / False]: The average energy consumption E_AV is based on the consumption measured for selected sets of input data.
Explanation: Average energy E_AV is empirical and calculated across representative benchmark input vectors. In contrast, worst-case energy E_WC must provide a guaranteed safe upper bound over all possible valid inputs.
Embedded Hardware [True / False]: Leakage current is negligible in terms of power consumption in modern embedded processors.
Explanation: In modern sub-micron CMOS fabrication technologies (<= 65 nm), static leakage current contributes up to 30% to 50% of total power dissipation. A classic distractor assumes only dynamic switching power matters.
VHDL IEEE 1164 [True / False]: VHDL uses a Hasse Diagram to determine the hierarchy of signals, according to which 'Z' is the strongest signal.
Explanation: In IEEE 1164 multi-valued logic, 'Z' denotes high impedance (floating/disconnected) and has weak driving strength. The strongest values are the forcing values ('0', '1', 'X'), which override 'Z' on a shared resolved bus.
VHDL IEEE 1164 [True / False]: A VHDL signal with a value of 'X' is stronger than a signal with a value of '0'.
Explanation: Both 'X' (forcing unknown) and '0' (forcing zero) have the exact same forcing drive strength class. Neither is stronger than the other; driving '0' and '1' concurrently resolves to 'X'.
Design Methodology [True / False]: Validation is the process of computing quantitative information of some key characteristics of a certain (possibly partial) design.
Explanation: Computing quantitative metrics (e.g., latency, energy, area) is Evaluation. Validation is checking whether a design satisfies its intended functional purpose and requirements ('building the right thing').
Real-Time Operating Systems [True / False]: A preemptive scheduler should not be used if the response times for external events have to be short.
Explanation: A preemptive scheduler is explicitly required when response times must be short, because it allows high-priority event-handling tasks to immediately preempt running lower-priority tasks. Non-preemptive schedulers introduce long blocking delays.
WCET Estimation [True / False]: A tight WCET estimate means WCET_EST >= WCET.
Explanation: A valid WCET estimate must be safe (WCET_EST >= WCET), and 'tight' means it minimizes the overestimation margin above the true WCET. An estimate with WCET_EST < WCET is unsafe and unacceptable.
WCET Estimation [True / False]: A tight WCET estimate means WCET_EST < WCET.
Explanation: If WCET_EST < WCET, the estimate underestimates the true worst-case execution time, which violates the fundamental real-time safety constraint and can cause missed deadlines.
Real-Time Operating Systems [True / False]: The priority ceiling protocol guarantees that, once a task has entered a critical section, it must be blocked by lower-priority tasks until its completion.
Explanation: Under PCP, once a task successfully enters a critical section, it can NEVER be blocked by lower-priority tasks. PCP eliminates chained blocking and prevents deadlocks entirely.
Communication Protocols [True / False]: CSMA/CA guarantees predictable response times to all bus participants.
Explanation: In CSMA/CA with bitwise non-destructive arbitration (such as CAN), deterministic response times are guaranteed ONLY for the message/node with the highest priority identifier. Lower-priority nodes can be starved indefinitely under heavy bus load.
Communication Protocols [True / False]: CSMA/CA guarantees predictable response times only for the highest priority participant.
Explanation: Because arbitration on CAN/CSMA/CA is non-destructive and priority-based, the frame with the highest priority identifier always wins bus access without backoff, ensuring a strictly bounded latency.
Specification & Modeling [True / False]: Any specification language has to have a notion of hierarchy.
Explanation: Hierarchy is a powerful modeling feature (e.g., in StateCharts), but it is not mandatory for all specification languages. Fundamental formalisms like elementary Petri nets, flat Communicating Finite State Machines, and basic Kahn Process Networks are non-hierarchical.
Specification & Modeling [True / False]: Kahn Process Networks (KPN) are determinate.
Explanation: KPNs are determinate because process communication is restricted to monotonic functions over unbounded FIFOs with blocking reads. For a given sequence of input data tokens, the output token sequence is mathematically unique and independent of execution speeds.
Specification & Modeling [True / False]: Kahn Process Networks are not Turing-complete.
Explanation: KPNs are Turing-complete because individual nodes can execute general-purpose Turing-equivalent code and communicate via unbounded queues, allowing them to simulate any Turing machine.
Embedded Hardware [True / False]: Scratchpad memories are typically more energy-efficient than caches.
Explanation: Scratchpad memories (SPMs) do not require tag memory arrays, comparator logic, or complex cache replacement controllers. Being software/compiler-managed and mapped into the physical address space, SPM access dissipates significantly less energy per read/write.
Real-Time Operating Systems [True / False]: Rate-Monotonic scheduling is not based on static properties.
Explanation: Rate-Monotonic Scheduling (RMS) is strictly based on static properties: fixed priorities are assigned offline inversely proportional to task periods (shorter period = higher static priority) and never change at runtime.
Petri Nets [True / False]: Condition/Event nets (C/E-Nets) can have tokens of different colors.
Explanation: C/E nets are elementary 1-safe Petri nets where places represent boolean conditions holding at most one uncolored (identical) token. It is Colored Petri Nets (CPNs) that introduce multi-valued, typed (colored) tokens.
Real-Time Operating Systems [True / False]: Earliest Deadline First (EDF) is optimal for periodic scheduling.
Explanation: EDF is an optimal dynamic-priority scheduling algorithm on uniprocessors for independent preemptive tasks whose relative deadlines equal their periods. If a task set can be scheduled by any algorithm, it can be scheduled by EDF up to 100% utilization (sum C_i / T_i <= 1).
Embedded Hardware [True / False]: Static power consumption is caused by charging capacitors when logic levels are switched.
Explanation: Charging and discharging load capacitors during logic switching causes dynamic power consumption (P_dyn = alpha * C_L * V_dd^2 * f). Static power is caused by leakage currents (subthreshold, gate oxide) flowing while transistors are stationary.
WCET Estimation [True / False]: The implicit path enumeration technique (IPET) can be used as a part of WCET estimation.
Explanation: IPET uses Integer Linear Programming (ILP) to maximize execution time over basic blocks subject to flow conservation and loop bound constraints, avoiding the exponential cost of explicitly enumerating all control flow paths.
Optimization [True / False]: If a variable voltage processor completes a task before the deadline, the energy consumption can be reduced.
Explanation: By applying Dynamic Voltage and Frequency Scaling (DVFS) to stretch task execution across the available slack time, the operating voltage V_dd can be reduced. Because dynamic energy scales quadratically with voltage (E proportional to V_dd^2), total energy drops substantially.
Real-Time Operating Systems [True / False]: A task set is schedulable under a set of constraints, if a schedule exists for that set of tasks and constraints.
Explanation: By definition, a real-time task set is schedulable if there exists at least one feasible schedule where all tasks execute to completion without violating any deadlines or resource constraints.
Real-Time Operating Systems [Concept Cloze]: In the Priority Ceiling Protocol, a given task i is delayed at most how many times by lower-priority tasks?
A) Never
B) Once
C) Twice
D) As many times as there are shared semaphores
Correct Answer: B) Once.
Explanation: A fundamental mathematical guarantee of PCP is that any task can be blocked by lower-priority tasks at most once during its execution (blocking duration is bounded by the duration of at most one critical section of a lower-priority task).
Specification & Modeling [Concept Cloze]: StateCharts [____] assumes a broadcast mechanism for variables and events.
A) explicitly
B) implicitly
C) never
D) selectively
Correct Answer: B) implicitly.
Explanation: StateCharts semantics implicitly assume a broadcast mechanism: any event generated by a state transition or action is globally and simultaneously visible across all orthogonal, concurrent components.
Fault Tolerance [Concept Cloze]: Faults in one Fault Containment Region (FCR) should [____] affect other regions.
A) always
B) rarely
D) temporarily
Correct Answer: C) never.
Explanation: By definition, Fault Containment Regions (FCRs) are structurally or electrically isolated zones designed to guarantee that faults originating inside one region never propagate to cause cascading failures in adjacent regions.
Embedded Hardware [Concept Cloze]: A Sample-and-Hold circuit is typically used to discretize a signal in the [____] domain.
A) value / amplitude
B) time
C) frequency
D) phase
Correct Answer: B) time.
Explanation: A Sample-and-Hold circuit samples the continuous-time signal at discrete clock ticks, discretizing strictly in the time domain. The subsequent quantizer / ADC discretizes the signal in the value/amplitude domain.
Real-Time Operating Systems [Concept Cloze]: A critical instant of a task is that time at which the release of the task will produce the [____] response time.
A) smallest
B) average
C) largest
D) nominal
Correct Answer: C) largest.
Explanation: The critical instant for a task occurs when it is released simultaneously with all higher-priority tasks, creating the worst-case scenario that produces its maximum (largest) response time.
Specification & Modeling [Concept Cloze]: In StateCharts, super-states S are called [____]-super-states if exactly one of the sub-states of S is active whenever S is active.
A) AND
B) OR
C) XOR
D) NOT
Correct Answer: B) OR.
Explanation: In StateCharts hierarchy, OR-superstates enforce mutual exclusion among substates (exactly one active substate). In contrast, AND-superstates represent orthogonal concurrency where all substates (one per region) are active concurrently.
Hardware & RTOS [Concept Cloze]: In real-time databases, the access times to magnetic hard disks are [____] predictable.
A) easily
B) highly
C) hardly
D) linearly
Correct Answer: C) hardly.
Explanation: Mechanical head seek delays, variable rotational latencies, and firmware track-reordering caches make hard disk access times non-deterministic and hardly predictable, which is why real-time systems prefer solid-state flash or deterministic SRAM/DRAM.
Dependability [Multiple Choice]: What is the fundamental mathematical distinction between Reliability R(t) and Availability A(t)?
A) Reliability is measured at a single time instant, while Availability is defined over an interval [0, t].
B) Reliability R(t) is the probability of continuous failure-free operation over interval [0, t], while Availability A(t) is the probability of correct operation at time instant t.
C) Availability applies only to hardware, whereas Reliability applies only to software.
D) Reliability includes repair time (MTTR), whereas Availability depends only on MTTF.
Correct Answer: B) Reliability R(t) is the probability of continuous failure-free operation over interval [0, t], while Availability A(t) is the probability of correct operation at time instant t.
Explanation: Reliability R(t) requires that zero failures occur throughout the entire interval [0, t]. Availability A(t) allows failures to have occurred, provided the system was repaired and is operational at instant t (A = MTTF / (MTTF + MTTR)).
Real-Time Concepts [True / False]: In a hard real-time system, completing a task after its deadline results in a degraded quality of service, but does not constitute a total system failure.
Explanation: In hard real-time systems, missing even a single deadline is considered a catastrophic failure that can cause loss of life or severe physical damage. Degraded quality of service with positive utility describes soft real-time systems.
Design Methodology [Multiple Choice]: Which three orthogonal representation domains form the axes of the Gajski-Kuhn Y-Chart?
A) Hardware, Software, Network
B) Behavioral, Structural, Physical/Geometric
C) Specification, Simulation, Verification
D) Time, Frequency, Energy
Correct Answer: B) Behavioral, Structural, Physical/Geometric.
Explanation: The Gajski-Kuhn Y-chart represents system synthesis across Behavioral (what it does), Structural (what functional blocks connect), and Physical/Geometric (how it is physically laid out on silicon) domains across varying abstraction levels.
Data Flow Modeling [True / False]: A Synchronous Data Flow (SDF) graph can be scheduled statically at compile-time with bounded buffer memory if and only if the balance equations Gamma * q = 0 yield a non-trivial positive integer repetition vector q and the graph contains no deadlocks.
Explanation: For an SDF graph to have a periodic, bounded-memory static schedule, token production and consumption rates across all edges must balance (Gamma * q = 0 has a rank equal to |Actors| - 1) and initial token delays must prevent circular deadlocks.
Petri Nets [True / False]: If an integer solution s exists for the Petri net state equation M_k = M_0 + C * s, the marking M_k is guaranteed to be reachable from initial marking M_0.
Explanation: The existence of a non-negative integer firing count vector s in M_k = M_0 + C * s is a necessary condition, but NOT a sufficient condition for reachability, because it does not guarantee that transitions can fire in an order without temporarily driving token counts negative.
Petri Nets [Multiple Choice]: In a Place/Transition net, what does it mean for a transition t to be L4-live (strictly live)?
A) Transition t can fire at least once in some execution sequence.
B) Transition t can fire infinitely often from the initial marking only.
C) Transition t is L1-firable (can be enabled) from EVERY marking reachable from M_0.
D) Transition t never consumes tokens from its input places.
Correct Answer: C) Transition t is L1-firable (can be enabled) from EVERY marking reachable from M_0.
Explanation: A transition is L4-live if it can never become dead, meaning that no matter what marking sequence the net reaches, there is always a valid continuation sequence that enables t again.
StateCharts [True / False]: When re-entering a hierarchical superstate via a Shallow History marker (H), all nested sub-states down to the leaf states are restored to their previously active configurations.
Explanation: Shallow History (H) restores the active sub-state only at the immediate hierarchical level; nested substates revert to their default arrows. It is Deep History (H*) that recursively restores the full hierarchy down to leaf states.
Discrete Event Simulation [True / False]: In VHDL and SystemC, a delta cycle advances physical simulation time by an infinitesimally small step delta_t > 0.
Explanation: A delta cycle advances execution order through evaluation and update phases without advancing physical simulation time at all (delta_t = 0), ensuring deterministic ordering of concurrent events.
A/D Discretization [Multiple Choice]: According to the theoretical Signal-to-Quantization-Noise Ratio formula SQNR approx 6.02 * N + 1.76 dB, what happens to the SQNR when the ADC resolution N is increased by 2 bits?
A) Increases by approx 3 dB
B) Increases by approx 6 dB
C) Increases by approx 12 dB
D) Doubles the noise power
Correct Answer: C) Increases by approx 12 dB.
Explanation: Each additional bit of resolution multiplies the number of quantization levels by 2, halving quantization step size Q and increasing SQNR by 6.02 dB. Thus, 2 additional bits increase SQNR by 2 * 6.02 approx 12.04 dB.
A/D Converters [Multiple Choice]: How many comparators are required by an N-bit Flash ADC compared to an N-bit Successive Approximation Register (SAR) ADC?
A) Flash requires N comparators; SAR requires 2^N comparators.
B) Flash requires 2^N - 1 comparators; SAR requires exactly 1 comparator.
C) Flash requires 2N comparators; SAR requires N comparators.
D) Both require exactly 2^N - 1 comparators.
Correct Answer: B) Flash requires 2^N - 1 comparators; SAR requires exactly 1 comparator.
Explanation: A Flash ADC performs conversion in a single cycle using 2^N - 1 parallel comparators (exponential hardware cost). A SAR ADC tests bits sequentially over N clock cycles using a DAC and a single comparator.
A/D Converters [True / False]: The conversion result of a Dual-Slope Integrating ADC is highly dependent on the absolute tolerance and temperature drift of the integration resistor R and capacitor C.
Explanation: The integration slope during the fixed run-up time T1 and de-integration slope during run-down time T2 both depend on the same 1/(R*C) factor. Because T2 = T1 * (V_in / V_ref), the R and C terms mathematically cancel out, making conversion independent of component drift.
Automotive Communication [Multiple Choice]: How does CAN bus arbitration resolve a collision between two nodes transmitting simultaneously?
A) Both nodes detect collision, abort transmission, and wait a random exponential backoff time.
B) Wired-AND logic ensures the dominant bit ('0') overrides the recessive bit ('1'); the node sending recessive detects dominant and yields immediately.
C) A master bus arbiter polls nodes sequentially via token passing.
D) Both messages are corrupted, requiring higher-layer CRC retransmission.
Correct Answer: B) Wired-AND logic ensures the dominant bit ('0') overrides the recessive bit ('1'); the node sending recessive detects dominant and yields immediately.
Explanation: CAN uses non-destructive bitwise arbitration. Because dominant '0' overrides recessive '1', the node with the lower numerical identifier (higher priority) continues sending without delay or frame corruption.
Embedded Memory [True / False]: DRAM cells use a 6-transistor bistable latch that retains data without refresh as long as power is applied, whereas SRAM stores charge on a capacitor.
Explanation: The definitions are inverted: SRAM uses a 6-transistor (6T) bistable latch that retains data continuously without refresh. DRAM uses a compact 1-transistor 1-capacitor (1T1C) cell where charge leaks off, requiring periodic refresh.
Embedded Memory [True / False]: Unlike hardware caches, a Scratchpad Memory (SPM) is mapped directly into the processor physical address space and has deterministic access latency.
Explanation: Scratchpad memory has dedicated physical memory addresses managed explicitly by the compiler or programmer, providing guaranteed single-cycle deterministic access times without cache tag lookups or miss penalties.
Real-Time Scheduling [True / False]: If a periodic task set has a total processor utilization U > n*(2^(1/n) - 1), it can never be scheduled feasibly under Rate Monotonic Scheduling.
Explanation: The Liu and Layland utilization bound is a SUFFICIENT condition, but NOT a necessary condition. Many task sets with utilization exceeding the bound (even up to 100%) are fully schedulable; exact feasibility must be checked with Response Time Analysis (RTA).
Resource Sharing Protocols [True / False]: Both the Priority Inheritance Protocol (PIP) and the Priority Ceiling Protocol (PCP) guarantee complete freedom from system deadlocks.
Explanation: PIP prevents unbounded priority inversion, but DOES NOT prevent deadlocks or chained blocking if tasks lock nested semaphores in conflicting orders. PCP guarantees complete deadlock freedom through its priority ceiling locking rule.
Fault Tolerance [Multiple Choice]: For a Triple Modular Redundancy (TMR) system with ideal majority voting and module reliability R(t), under what condition is the TMR system more reliable than a single non-redundant module (R_TMR(t) > R(t))?
A) For all values of R(t) in [0, 1]
B) Only when R(t) > 0.5
C) Only when R(t) < 0.5
D) Only when R(t) = 1.0
Correct Answer: B) Only when R(t) > 0.5.
Explanation: The reliability equation is R_TMR = 3*R^2 - 2*R^3. Solving 3*R^2 - 2*R^3 > R yields (2R - 1)(R - 1) < 0, which holds strictly when R > 0.5. If module reliability drops below 0.5, TMR is worse than a single simplex module.
Fault Tolerance [Multiple Choice]: What is the minimum number of nodes n required in a distributed system to reach consensus in the presence of m arbitrary (Byzantine) faulty nodes?
A) n >= 2m + 1
B) n >= 3m
C) n >= 3m + 1
D) n >= 2^m
Correct Answer: C) n >= 3m + 1.
Explanation: Pease, Shostak, and Lamport proved that to achieve Byzantine agreement without digital signatures against m arbitrary/malicious faults, the network must contain at least 3m + 1 independent processors and execute at least m + 1 rounds of message exchanges.
Static Cache Analysis [Multiple Choice]: In static WCET cache analysis under LRU replacement, what are the join operations used at control-flow merge points for Must Analysis (hit prediction) and May Analysis (miss prediction)?
A) Must uses Union + min age; May uses Intersection + max age
B) Must uses Intersection + max age; May uses Union + min age
C) Both use Union + max age
D) Both use Intersection + min age
Correct Answer: B) Must uses Intersection + max age; May uses Union + min age.
Explanation: Must Analysis safely predicts guaranteed cache hits by taking the intersection of blocks present in all incoming paths with their maximum age. May Analysis safely predicts guaranteed misses by taking the union of blocks with their minimum age.
Optimization [Multiple Choice]: In Dynamic Voltage and Frequency Scaling (DVFS), what is the 'Critical Frequency' (f_crit)?
A) The maximum clock frequency supported by the silicon before thermal runaway occurs.
B) The clock frequency below which further frequency reduction increases total energy consumption due to accumulated static leakage energy.
C) The frequency at which dynamic power exactly equals switching frequency.
D) The Nyquist frequency of the on-chip clock generator.
Correct Answer: B) The clock frequency below which further frequency reduction increases total energy consumption due to accumulated static leakage energy.
Explanation: Below f_crit, the extra execution time required by a slower clock causes static leakage power (P_stat * t_exec) to accumulate more energy than is saved in dynamic power, meaning running slower actually wastes energy.
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