What are characteristics of a general-purpose processor?
-> Can execute a wide range of instructions and application
-> highest flexability among implementaion alternatives
drawbacks:
-> high power conumption due complex architecture and memory hierarchy
-> unpredictable access to shared resources (caches, buses) which affects timing
-> in general poor predictability, not suitable for embedded systems with hard or firm real-time deadlines
What are characteristics of special-purpose processors?
-> opimized for certain tasks or domains (e.g. arithmetic tasks)
-> Trade generality for efficiency by having specialized hardware or specific instruction sets
They are a good choice for embedded systems that have well defined and stable requirements.
What special purpose processors do you know?
-> micro-controllers
-> digital signal processors (DSP’s)
-> application specific instruction set processors (ASIP’s)
What is programmable hardware?
-> Hardware that can be configured and reconfigured at runtime to implement different functionalities or architectures.
e.g. FPGA’s (Field programmable gate array) or adaptive compute acceleration platforms (ACAP’s)
What are advantages and disadvantages of programmable hardware?
advantages:
-> offers high efficiency and determinism
-> reprogramming the architecture ensures compatibility to changing standards or requirements
-> dedicated resources to create custom I/O interfaces
disadvantages:
-> high cost
-> lower density than fixed hardware
What are application sepcific integrated circuits (ASIC’s)? What are advantages and drawbacks?
Custom designed circuits that implement specific functionalities or architectures in hardware. Typically high performance or low-power applications with high market volumes.
-> ultimate speed (lol des steht wirklich so in den folien)
-> energy efficiency
-> high design costs
-> high production costs (e.g. masking)
-> no flexability
-> high risk of obsolence or failure due to technology scaling and environmental factors
How does the power consumption in CMOS-technology compute?
Dynamic power consumption is caused by charging capacitors when logic levels switch
Static power consumption is mainly caused by leakage current. Also consumed in absence of clock signals!
red = dynamic power, blue = static power
How does changing the voltages level of supply- and threshhold-voltage influence the circuit delay?
Increasing Vdd -> runtime reduces linearly, power consumption increases quadratically!
Decreasing Vth -> increases speed, but increases leakage current!
Which degrees of freedom are there for power reduction?
Reducing Vdd
Vdd/2 -> P/4!
But also slows down clock!
Slower clock
slower design -> increase parallelism
combine with voltage reduction
lower capacitance
reduces device size
reduce switching activity
What is clock gating?
Used to reduce switching activity.
Cuts the clock to a group of inactive modules, which lowers their dynamical power consumption
How are different power domains used?
Dedicated power rails supplied by e.g. 2 voltage sources -> switch between active and retention voltage source
less power consumption in retention state!
additional retention state
useful to switch to e.g. low-power mode idle mode and quickly switching back to active state
What is dynamic voltage and frequency scaling (DVFS)?
Dynamic selection of the optimal frequency and voltage in order ro execute the task within the required amount of time.
-> the system always runs at the lowest operating performance point (OPP) that meats the performance requirement at a given time
What is dynamic power management (DPM)?
The systems runs at the highest OOP in order to complete tasks quickly. Automatic switch to idle power mode, to consume minimum possible power.
-> Maximizes idle time to reduce power
-> Wake-up latency conditions (due to transitions) need to allow it
What is parallelism?
reduces power consumption by running parallel operations at lower voltages instead of running sequential ones at high voltage
What does Dennard Scaling postulate? Why did it end around 2006? What is the consequence of the end of Dennard scaling?
Dennard Scaling states that as transistors get smaller, their power density stays constant, so power use remains proportional to area, allowing frequency to increase without increasing power.
It ended because voltage scaling couldn't keep up with shrinking transistors, leading to increased power density and heat that couldn’t be efficiently dissipated.
The main consequence is the "power wall," which limits clock speed increases to around max. 4 GHz, shifting focus to multi-core processors and parallel computing for performance gains.
What is dark silicon?
Many cores result in higher switching capacities. In order to still meet power-requirements only a part of the circuit can be active. The inactive area is called dark silicon.
-> portions of the chip are turned off
e.g. mobile phone -> if everything would be active at once, the heat would burn our hand and the battery drain too fast.
What is Amdahl’s law?
It predicts the theoretical speedup when using multiple procesors?
It limits performance gain of parallel processing -> there always is a natural limit, as some tasks can not be parallelized!
What do the letters in Amdahl’s law mean?
L -> theoretical speed up
s -> speedup factor of the task being accelerated
p -> proportion of the overall task that can be accelerated
What is high performance computing?
The ability to perform complex and intensive computations in a short time.
Explain multicore architectures and their advantage and drawbacks.
-> uses multiple processor cores on a single chip which executes multiple tasks or threads in parallel
advantage:
-> Can significally increase execution speed of software that supports multithreading techniques
-> requires complex coordination of threads
-> some tasks are not parallelizable
-> use of multiple cores may not be helpful depending on the amount of cores used.
Explain Instruction level parallelism (ILP’s) and their advantage and drawbacks.
Computing architectures in which multiple operations can be performed in parallel with an own set of resources are called ILP’s.
Example: Scalar pipelining devides an instruction into several stages and executes them in a pipeline. allowing multiple instructions to be processed simultaneously.
What is the difference between VLIW ,RISC and CISC?
VLIW (Very long instruction word):
encodes paarallel operations in one long word, each instruction controlling one functional unit. Reduces complexitiy of hardware at runtime but shifts parallelism detection to compiler
RISC (Reduced instruction set computer):
aims to reduce the cycles per instruction. RISC does not use microcode, which makes cycles faster, but requires more code to perform the same instruction with CISC. Mostly operates on registers and very rarely on memory.
CISC (Complex instruction set computer):
aims to reduce the number of instructions that a program executes
What is an instruction set architecture? List two key differences between Complex Instruction Set Computers (CISC) and Reduced Instruction Set Computers (RISC). Specify also which of the two architectures is more suitabe to implement pipelines.
Instruction set architecture: Is an abstract model that generally defines how software controls the CPU
RISC:
-> Small and simple instructions, multiple instructions which CISC could do in one
-> Instructions are executed in a single clock cycle
CISC:
Which of these techniques is/are linked to the multiply/accumulate and zero-overhead loop instructions in a digital signal processor?
-> Use of multiple memory banks (to simplify parallel fetches)
-> Use of direct operations on address registers
-> Use of very long instruction words
-> Use of heterogeneous registers
-> Use of modulo addressing
-> Use of indirect memory addressing
Which of the following statements is/are false?
-> Superscalar architectures seek to improve the parallel instruction rate
-> Superpipelining architectures seek to improve the sequential instruction rate
-> With ILP, a faster machine can run a given software faster without the need to modify its code
-> Instructions can be executed out of order in some ILP architectures
-> VLIW processors do not belong to ILP architectures
Which of these statements about RISC/CISC architectures is/are correct?
-> The aim of RISC machines is to reduce the number of instructions executed by a program
-> Instructions in a CISC machine take approx. only 1 clock cycle to execute
-> CISC machines are typically characterized by a larger number of registers than RISC ones
-> The CPI of RISC architectures is very regular, which simplifies pipelining
-> Programs written for CISC machines have, in average, a higher instruction count
A program contains a ‘load’ instruction before a ‘store’ instruction to the same register. Which type of data hazard does this represent?
-> RAW hazard
-> WAR hazard
-> RAR hazard
-> WAW hazard
-> WWW hazard
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