Which term describes the process of checking whether or not a certain design is appropriate for its purpose, meets all constraints, and will perform as expected?
A) Verification
B) Validation
C) Synthesis
D) Simulation
Explanation: Validation checks whether the design satisfies the customer's actual requirements and intended purpose (building the right system). Verification checks compliance with formal specifications (building the system right).
Petri nets are a particularly suitable modeling language for describing which type of systems?
A) Distributed systems
B) Purely sequential single-cycle systems
C) Continuous-time analog circuits
D) Centralized single-core schedulers
Explanation: Petri nets excel at formally modeling distributed, concurrent, and asynchronous systems.
For a given set of input data, Kahn Process Networks (KPNs) will always generate the same results, independently of the:
A) Number of FIFO queues
B) Speed of the nodes
C) Sequence of incoming tokens
D) Functional operations performed
Explanation: Kahn Process Networks are deterministic. The execution results are completely independent of computation or communication speeds.
In embedded systems communication, asynchronous message passing with finite capacity may primarily lead to:
A) Deadlocks
B) Buffer overflows
C) Clock synchronization errors
D) Static timing violations
Explanation: In asynchronous communication, the sender continues without waiting for the receiver. If message production outpaces consumption, finite queues suffer buffer overflows (exam trap: deadlocks typically arise from blocking/synchronous protocols).
In digital circuits, Dynamic Power Consumption is caused by charging and discharging capacitances when logic levels are:
A) Switched
B) Held constant
C) Gated off entirely
D) Biased in static mode
Explanation: Dynamic power dissipation occurs during switching activity (P = α · C · Vdd² · f) when parasitic capacitances are charged and discharged.
Rate Monotonic (RM) scheduling is an optimal fixed-priority algorithm used for scheduling:
A) Independent periodic tasks
B) Sporadic aperiodic tasks with arbitrary deadlines
C) Heavily interdependent blocking tasks
D) Non-preemptive best-effort tasks
Explanation: Classic Rate Monotonic scheduling strictly assumes independent, periodic tasks whose relative deadlines equal their periods.
In real-time bus and communication architectures, TDMA resources are characterized by having what kind of timing behavior?
A) Stochastic timing behaviour
B) Deterministic timing behaviour
C) Contention-based non-deterministic timing
D) Unpredictable jitter behaviour
Explanation: Time Division Multiple Access (TDMA) statically allocates predefined time slots to participants, guaranteeing deterministic transmission latency.
When creating a StateChart, a super-state is considered an OR-state if:
A) All of its sub-states are active simultaneously
B) Exactly one of its sub-states is active whenever the super-state is active
C) Any random combination of sub-states can be active
D) It only contains history mechanisms without transitions
Explanation: In StateCharts, an OR-state represents exclusive hierarchy (only one sub-state active at a time), whereas an AND-state represents concurrent/orthogonal states.
In hardware description languages like VHDL, processes typically represent:
A) Operating system threads
B) Hardware components
C) Software routines
D) Dynamic memory allocations
Explanation: VHDL processes are concurrent blocks modeling concurrent hardware entities (e.g., registers, combinatorial logic circuits).
A Sample-and-Hold circuit is typically used to discretize an analog signal in the:
A) Value domain
B) Time domain
C) Frequency domain
D) Spatial domain
Explanation: Sample-and-Hold discretizes a continuous signal in time (sampling points). Quantization (performed by the ADC) discretizes the signal in the value domain.
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